Computer systems are well known in the art. In particular, a computer system adhering to the “IBM PC” standard is well known in the art. Referring to FIG. 1, there is shown a computer system 10 of the prior art. The computer system 10 conforms to the “IBM PC” architecture. The system 10 comprises typically a motherboard 12 on which are mounted a variety of components such as a processor 14, such as a Pentium microprocessor made by Intel Corporation, a memory controller hub (MCH) chip 16, and a 10 controller hub (ICH) chip 18. The MCH 16 and the ICH 18 are known as chipsets and can be obtained from Intel Corporation. The motherboard 12 also comprises a non-volatile memory device 20 which is typically for storing main system BIOS. The MCH chip 16 also interfaces with or may be integrated with (i.e. embedded within) a graphics controller chip 62, which outputs its video signal to a video display port, typically a VGA port and to a video device (not shown), such as an LCD display or CRT display. The foregoing system is described and is disclosed in U.S. Pat. No. 6,421,765. See also U.S. Pat. No. 6,330,635.
Intel Corporation, a developer of the MCH chip 16, also developed the ICH chip 18 which has a particular feature known as a low pin count (LPC) bus. See, for example, U.S. Pat. No. 5,991,841. The ICH chip 18 has an LPC bus interface 19 which interfaces with an LPC bus 66, which communicates with the BIOS memory device 20. At the time that Intel Corporation introduced the LPC bus 66, it disclosed that the LPC bus 66 is operable in accordance with the standard as disclosed in FIG. 2. This is also disclosed in U.S. Pat. No. 5,991,841. The LPC bus 66 comprises four signal lines between the ICH chip 18 and the peripheral devices such as the BIOS memory device 20. Along the four signal lines, designated as LAD [3:0], are supplied address, data and control fields that are multiplexed. As shown in FIG. 2, the initial field for the LAD bus is a start field. This is then followed by the address, data and control fields. In addition, the LPC bus 66 has LCLK and LFRAME# control signals.
From time to time, a need arises for the ICH chip 18 through the LPC bus interface 19 to the bus 66 to interface with a plurality of BIOS memory chips 20. In the prior art, the manner of connecting a plurality of BIOS memory chips 20 to an LPC bus 66 is shown in FIG. 3. Since the bus 66 is the only bus that connects in common to all of the BIOS memory chips 20 and it supplies data fields, address fields, and control fields in common to all the chips 20, there must be a mechanism by which one BIOS chip 20 is distinguished from another. In the prior art this is accomplished by having each of the BIOS chips 20 having four additional pins which are “strapped”, i.e., a common technique to tie down the pins to either VCC (a source of power supply) or VSS (ground). As shown in FIG. 3, for example, BIOS chip 20A has all four of its device ID pins connected to VSS, thereby creating the combination of “0000” bit pattern. Similarly, BIOS chip 20C has its four device ID pins connected to VSS, VSS, VCC, and VSS, creating a bit pattern of “0010”. Finally, since there are four device pins, there is the possibility of the LPC bus 66 supporting up to 16 BIOS chips 20. Thus, the “last” device, BIOS chip 20P, has all of its four device pins connected to VCC, resulting in a bit pattern of “1111”.
The use of the device pins in the prior art BIOS chips 20 poses at least two problems. First, four additional pins must be provided to each chip 20 thereby increasing the cost. This is also contrary to the philosophy of a “low pin count” bus. Second, the identification for each device cannot be known until it is actually mounted on the motherboard 12 and the device ID pins tied to specific voltages, either ground or VCC. Since the layout of the wiring of either ground or VCC on a motherboard 12 may already be set, it may be difficult to place additional BIOS chips 20 having the desired device ID.